Crash in 05_01_fifo_with_counter_baseline

[atarasenko2]

Running ./run_using_iverilog_under_linux_or_macos_brew.sh crashes with error:

./run_using_iverilog_under_linux_or_macos_brew.sh: line 53: 54512 Abort trap: 6           vvp a.out >> log.txt 2>&1

A fix is to replace & with && in lines 47-49 of fifo_monitor.sv:

assert (~ (~ empty
           && queue.size () != 0
           && read_data != queue [0]));

Is it for everyone or just me?

Mac OS Ventura 13.6.6 (22G630) Icarus Verilog version 12.0

[yuri-panchul]

This is a very well-known bug dated in C from the year 1970. The main difference between "a & b" and "a && b" is: if "a" is false, "b" is always evaluated in "a & b" case but is not evaluated in "a && b" case. In other words, a && b acts as if:

if (! a) result = 0; else result = b;

In this particular example, the simulator is trying to access element 0 of an empty queue which causes memory error. Ideally, the simulator should caught it itself and make an error "queue is empty" but many simulators are not well written or omit such check for efficiency (such as Cadence Xcelium and apparently Icarus).

The solution is to go through all the code in the repository (+ basics-graphics-music) and fix all such places.

[atarasenko2]

Thanks for the explanation

[max-kudinov]

I've fixed this in a private version of this repo, but it's currently WIP and not ready for merge with public. When it'll be ready we'll merge the fix.

Thanks for noticing this issue.