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yuri-panchul / systemverilog-homework

SystemVerilog language-oriented exercises
MIT License
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Macroed testing #21

Closed samedhi closed 1 month ago

samedhi commented 2 months ago

Up for consideration, this basically does something similar with section 2 to what was done in section 1.

I also added a small macro that basically prints, binary, decimal, or hex with the literal "symbol" on the left and the symbols value on the right, separated by a colon. I think this is better as it makes it more difficult to make errors in terms of printing a different value than the symbol you meant to print.

I played with short circuiting the test but the only way I can see to do that is to use $fatal, and that seems to return a bunch of annoying text in the stdout. I have distinguished the "SUCCESS" $finish from the "FAIL" $finish by doing $finish(1) for the failures.

max-kudinov commented 1 month ago

I've added these changes manually to the private repo, except short circuiting the test, because our shell scripts have changed drastically and I don't have time yet to implement that.

Would be nice if you could take a look at new scripts.