Closed p-krishnat closed 7 years ago
I have one pulse as shown in fig. Pulse width is 10 to 25 us. But next pulse will come after 100 ms.
I need to find peak of each pulse. I have reference peak value. I need to generate error send to DAC module.
In my current code,
If I take one sample and check whether peak or not, and calculate error send to DAC,
this code takes 35 us time.That means pulse is gone.
How should I tackle this situation
I have one solution, I want suggestion from you , whether it is feasible or not??
ADC0 and ADC1- same pulse as input
ADC0-Comparator
ADC1-uDMA module
I will configure my ADC0 module for digital comparator for HIGH band in always mode.
I will start my uDMA module to store ADC1 samples until my comparator output is High.
Once comparator output is LOW, I will start find peak out of stored samples & generate error send to DAC module.
@p-krishnat I have no idea how to help you with this, and this isn't an issue with the repository, sorry.
I think your best shot are the 43oh forums: http://forum.43oh.com/
I have one pulse as shown in fig. Pulse width is 10 to 25 us. But next pulse will come after 100 ms.
I need to find peak of each pulse. I have reference peak value. I need to generate error send to DAC module.![1](https://cloud.githubusercontent.com/assets/25381765/22363237/e452ab94-e48e-11e6-82ef-7f1c2c69851d.jpg)
In my current code,
If I take one sample and check whether peak or not, and calculate error send to DAC,
this code takes 35 us time.That means pulse is gone.
How should I tackle this situation
I have one solution, I want suggestion from you , whether it is feasible or not??
ADC0 and ADC1- same pulse as input
ADC0-Comparator
ADC1-uDMA module
I will configure my ADC0 module for digital comparator for HIGH band in always mode.
I will start my uDMA module to store ADC1 samples until my comparator output is High.
Once comparator output is LOW, I will start find peak out of stored samples & generate error send to DAC module.