Missing FAKE INSTRUCTIONS like "ex bc, hl" and other combinations that exploit "ex (sp), rr"

[sromeroi]

The following missing fake instructions are not described in sjasmplus documentation (so they're probably not implemented):

ex bc, hl => push bc : ex (sp), hl : pop bc
ex bc, ix => push bc : ex (sp), ix : pop bc
ex bc, iy => push bc : ex (sp), iy : pop bc
ex af, hl => push af : ex (sp), hl : pop af
ex af, ix => push af : ex (sp), ix : pop af
ex af, iy => push af : ex (sp), iy : pop af
ex de, ix => push de : ex (sp), ix : pop de
ex de, iy => push de : ex (sp), iy : pop de

Example:

ld bc, $1234
ld hl, $5678
push bc
ex (sp), hl    ; hl = $1234
pop bc         ; bc = $5678

Could be written as:

ld bc, $1234
ld hl, $5678
ex bc, hl

Could you please include them in sjasmplus?

[ped7g]

The ex bc,hl could be also push hl : ld l,c : ld h,b : pop bc which is 1 byte longer but -11T faster and in case you have single spare register you can write it as 6x ld to have 24T total instead of 29T (or yours 40T).

I feel a bit dubious about these, but I guess most of the fake instruction already are dubious, so that's not a good counter argument. I'm more like surprised you are even missing these, that was unexpected for me. :) (how comes, did you run into the need of this in some real project?)

But I guess there's little harm to add them, probably in the faster-but-longer variant doing ld where possible? If anyone else has opinion/idea about these, please share, so it's not just me vs OP.

[sromeroi]

Thanks for you quick response.

I just came across those combinations while reading/watching Z80 ASM tutorials, and found out that they were not available among the existing Fake Instructions.

I agree about your -11T+1b combination, it's a better tradeof to save 11 t-states for a single byte. Thanks!

[ped7g]

So I have been pondering about this for a while, also discussed it with other users and contributors, and these ex feels not "attractive enough" for us to add them, we can't recall any good use cases from our experience of writing ZX SW, usually when you long for ex bc,hl the answer is to write the code in different way to not need it.

The tricky part is that ex de,hl is only one byte and only 4T (as it's technically just flipping single bit inside CPU, not doing much work, so for anyone not familiar with Z80 ISA having ex bc,hl on hand would look similarly cheap, while it's lot more costly in the form of fake instruction. And it's using also stack which is another "not attractive" feature.

If you would go through current list of fake instructions, you could easily find few more questionable, which could be rejected by similar reasoning, so please understand this is rather subjective ruling, but I don't see a way how to make this process more objective. I hope you will understand it as it is. I'm definitely glad you did raise this, could be still helpful info for people who would look for it.

In the end, it's reasonable easy to add your own macro if you really need instruction like this, but I would be surprised if you would need this often, we were discussing it among people who delivered tens+ ZX projects over decades and nobody was able to recall good use case.

[sromeroi]

Thanks anyway for considering my request.