zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Bug when a module with parameter type instantiate another module with two parameter types #106

Closed b1f6c1c4 closed 4 years ago

b1f6c1c4 commented 4 years ago

Tested on

> sv2v --version
sv2v v0.0.4 (a7673c5)

Input:

module M0 #(parameter type T1 = logic, parameter type T2 = logic) ();
endmodule

module M1 #(parameter type T1 = logic);
  localparam int unsigned L0 = 1;
  localparam int unsigned L1 = L0 + 1;
  M0 #(.T1(T1), .T2(logic [L1-1:0])) inst ();
endmodule

Output:

module M0_9A0C4;

endmodule
module M0_F79F1;
    parameter type T2_L1_type;
    parameter T2_L1_type T2_L1 = 0;
endmodule
module M1_AA443;
    localparam [31:0] L0 = 1;
    localparam [31:0] L1 = L0 + 1;
    M0_F79F1 #(
            .T2_L1_type([31:0]),
            .T2_L1(L1)
    ) inst();
endmodule

The two occurrences of T2_L1_type surprised for me.

Might be related to #90 ?

zachjs commented 4 years ago

This should be fixed as of ff166df59c7b14195a9561259493a3b2480c2e3f. The implicit type ([31:0]) in the generated type parameter (.T2_L1_type([31:0]),) was previously considered "not ready" for substitution, but this was not intended.