zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Bug using bit selection in function in package #107

Closed b1f6c1c4 closed 4 years ago

b1f6c1c4 commented 4 years ago

Input:

package P;
  function automatic logic [7:0] f(input logic [2:0] p);
    logic [7:0] r;
    r = '0;
    r[p+:2] = '1;
    return r;
  endfunction
endpackage

module M (input [2:0] p, output [7:0] q);
  assign q = P::f(p);
endmodule

Output from sv2v v0.0.4 (d88c516):

module M (
    p,
    q
);
    input [2:0] p;
    output [7:0] q;
    function automatic [(2 * $bits(type(r[0]))) - 1:0] sv2v_cast_A9095;
            input reg [(2 * $bits(type(r[0]))) - 1:0] inp;
            sv2v_cast_A9095 = inp;
    endfunction
    function automatic [7:0] P_f;
            input reg [2:0] p;
            reg [7:0] r;
            begin
                        r = 8'b0;
                        r[p+:2] = sv2v_cast_A9095(1'sb1);
                        P_f = r;
            end
    endfunction
    assign q = P_f(p);
endmodule

The function sv2v_cast_A9095 contains syntax error (type(...)).

zachjs commented 4 years ago

Thank you for spotting this issue and providing a test case! This should be fixed as of db21869e69272dd16fffa02c1ae7fca0d8c889ad.