Closed b1f6c1c4 closed 4 years ago
Input:
module M(input c); logic [31:0] w0 = c ? '0 : $unsigned(0); logic [31:0] w1 = c ? '0 : unsigned'(0); endmodule
Output from sv2v v0.0.4 (cc9f7f4):
sv2v v0.0.4 (cc9f7f4)
module M (c); input c; wire [31:0] w0 = (c ? $bits(type($unsigned))'(1'sb0) : $unsigned(0)); wire [31:0] w1 = (c ? $bits(type($unsigned))'(1'sb0) : $unsigned(0)); endmodule
Thanks for another report! This should be fixed as of 03b6ece939157f6724882ad010e63e0ea1882c9d.
Input:
Output from
sv2v v0.0.4 (cc9f7f4)
: