zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Bug when using $unsigned in ?: #109

Closed b1f6c1c4 closed 4 years ago

b1f6c1c4 commented 4 years ago

Input:

module M(input c);
  logic [31:0] w0 = c ? '0 : $unsigned(0);
  logic [31:0] w1 = c ? '0 : unsigned'(0);
endmodule

Output from sv2v v0.0.4 (cc9f7f4):

module M (c);
    input c;
    wire [31:0] w0 = (c ? $bits(type($unsigned))'(1'sb0) : $unsigned(0));
    wire [31:0] w1 = (c ? $bits(type($unsigned))'(1'sb0) : $unsigned(0));
endmodule
zachjs commented 4 years ago

Thanks for another report! This should be fixed as of 03b6ece939157f6724882ad010e63e0ea1882c9d.