zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Ergonomics improvement: trailing commas [feature request] #136

Closed chrivers closed 3 years ago

chrivers commented 3 years ago

There seems to be no good consensus on strictness vs ergonomics when it comes to trailing commas in parameter lists.

For example, this test case:

module foo #(
    parameter THING = 0,
)();

endmodule

This is rejected by iverilog and sv2v, but happily accepted by yosys.

For those using sv2v as a frontend to (for example) yosys, it would be great if sv2v could accept trailing commas like this, and just not output them. That would make a good workflow for humans, and be fully compatible with the next step in the pipeline.

zachjs commented 3 years ago

Sorry for the delay in addressing this! I've added support as of 5a8801a45f4ebe729ea88a85f38425d04799acf9. Please let me know what you think!

chrivers commented 3 years ago

Seems to work great - thank you!