Some module syntax is not accepted

zachjs / sv2v

SystemVerilog to Verilog conversion

BSD 3-Clause "New" or "Revised" License

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Some module syntax is not accepted #146

Closed flaviens closed 3 years ago

flaviens commented 3 years ago

Hi!

I've encountered some Verilog file that could not be parsed by sv2v: aes_128.sv (line 32) of AES_T100 (and probably others as well). You can find the file here: https://www.trust-hub.org/#/benchmarks/chip-level-trojan.

It seems to be due to a hole representing an unusued output signal in a module instance with ordered signal connections.

zachjs commented 3 years ago

I've added support for unconnected ports in ordered port connections as of 801955ffab6ce4d89e1a274aeb34ffce6a771e21. This is done in a way which I believe is logically consistent with the support for trailing commas added previously.

I've confirmed the reference file now converts cleanly. Please let me know if this works for your use case!

flaviens commented 3 years ago

Great, perfect! Thank you for your work!