Closed flaviens closed 3 years ago
Is there any chance you could upload the input file? This would speed things up on my side.
Sure! Just give me a minute
On both the uploaded file and the original source, I run into a few different issues, but not yet the one you've listed above.
Foo'{ x: 1, y : 2}
, but this has now been fixeddefs_div_sqrt_mvp
and riscv_defines
in the global scope. These packages both export definitions for C_PC
, which causes sv2v to (accurately) flag usages of C_PC
as ambiguous. With the conflicting imports residing in the same file, most tools flag the ambiguity. If they are in separate files, it appears most other tools use whichever definition was imported in the earliest file (which is probably not what you want), while at least one vendor appears to implicitly give the wildcard import in the current file higher precedence. However, sv2v does not currently implement any special behavior when dealing with package imports based on the split of the source files.axi_cdc_src
in axi_lite_cdc_src_intf
refers to ports src_req_o
and src_resp_i
, which do not exist in axi_cdc_src
(the directionality is flipped).Hi Zach, thank you warmly for your amazingly fast reaction and the new feature! Also thanks for the interesting explanations.
Now after fixing all the mentioned and applying the fresh sv2v version, I finally (sadly) run again into the aforementioned issue:
sv2v: src/Convert/Scoper.hs:480:17-59: Non-exhaustive patterns in Variable Local
newType
newName
[]
Nil
You can reproduce it by applying sv2v to the updated file: https://github.com/flaviens/pickled_pulpissimo/blob/master/pickled.sv
I've found and fixed a couple more issues, but at least a few still remain. I'll share a more complete progress update sometime tomorrow.
I've made some solid progress, and have fixed the following issues:
While a few other issues may still remain, I have encountered an interesting case in the source. The module axi_to_reg
uses logic
as the default for certain type parameters which could only reasonably be structs. The module isn't used anywhere in the available source, so sv2v makes the default instantiation of the module available in the output, because such modules could be used externally. However, the default instantiation of this module is naturally garbage, because logic
isn't a struct with fields.
I imagine most tools would error on such an input as the following. sv2v doesn't currently catch this as invalid, but I'd argue the source should be fixed regardless.
module bad;
parameter type T = logic;
T x;
assign x.y = 1;
endmodule
module top;
initial $display("hi");
endmodule
Hi Zach, Congratulations for all this work! The pickled file indeed passes through sv2v now !
However, there remain some syntax errors in the sv2v output, as Verilator reports. I updated the repository to help you: https://github.com/flaviens/pickled_pulpissimo/ (you may want to re-clone it because it has been rebased).
Just make sure you have Verilator in your path, and make
.
I will look into a pair of issues related to unbased unsized literals. In the meantime, I think you may be interested in setting `default_nettype none
. Currently, there are wires like s_int_datasize
which are implicitly created as size 1, despite being assigned a wider value.
I've also noticed the latest pickled file is missing the boot_rom
module, which especially needs to be present because it has an interface port.
Hi Zach!
I encountered an issue with working with sv2v on the PULPissimo SoC. My sv2v version is currently
sv2v v0.0.7-114-g836536c
.Prerequisites
https://github.com/pulp-platform/bender.git https://github.com/zarubaf/morty.git
Steps to reproduce
Outcome
which corresponds to
Also, once I received today with the same pickled file (but cannot reproduce it):
Please let me know if you need more indications. Your work is much appreciated! :)