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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Support for datatypes on the wire nettypes #160

Closed chiraag closed 3 years ago

chiraag commented 3 years ago

I was trying to work on a design with the following syntax:

wire logic x = 1'b0;

This is error message I get:

sv2v: takeIdent didn't find identifier: [DTType rtl/top.sv:11:12 logic,DTIdent rtl/top.sv:11:14 "x",DTAsgn rtl/top.sv:11:20 = Nothing 1'b0]
CallStack (from HasCallStack):
  error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:496:20 in main:Language.SystemVerilog.Parser.ParseDecl

I believe this is valid syntax.

zachjs commented 3 years ago

What version are you using? This feature is implemented on master.

chiraag commented 3 years ago

I was using the v0.0.7 binary release? Have there been a ton of updates since then? If yes, I can try using the binary from the latest Github build action.

zachjs commented 3 years ago

Yes, please give that a shot. v0.0.7 is pretty old at this point. I will look into making at least quarterly releases in the future.

chiraag commented 3 years ago

Works with 1e6fa7b