task arguments are not translated correctly

[mio-19]

SuperVerilog source:

    task automatic test_add_frac(frac_t a, frac_t b);
        frac_t c = frac_add(a, b);
        $display("%f + %f = %f", frac2real(a), frac2real(b), frac2real(c));
    endtask

sv2v 0.0.8 output

    task automatic test_add_frac;
        reg [31:0] a;
        reg [31:0] b;
        reg [31:0] c;
        begin
            c = frac_add(a, b);
            $display("%f + %f = %f", frac2real(a), frac2real(b), frac2real(c));
        end
    endtask

Correct output would be

    task automatic test_add_frac;
        input reg [31:0] a;
        input reg [31:0] b;
        reg [31:0] c;
        begin
            c = frac_add(a, b);
            $display("%f + %f = %f", frac2real(a), frac2real(b), frac2real(c));
        end
    endtask

[zachjs]

Thanks for filing this issue! It should be fixed as of 4ded2a598d8827bea0fcd9264e5af3c7846654dc.