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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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One issue was good in V0.07 but failed in V0.08 #168

Closed stitchlibar closed 3 years ago

stitchlibar commented 3 years ago

It complains that sv2v: test.sv:14:51: Parse error: declaration missing type information CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:599:26 in main:Language.SystemVerilog.Parser.ParseDecl

function automatic signed [2:0] p4vs(input en,err,[1:0]d); reg signed [2:0] sym; begin case(d[1:0]) 2'b00: sym = 3'b101; default: sym = 3'b111; endcase // case (d[1:0]) if(!en) p4vs = 3'd0; else p4vs = err? sym : -sym; end endfunction

zachjs commented 3 years ago

Thanks for this report! This should be fixed in 7ccab1c70a1236a078e9f913589de8a5a22d391b. Please let me know if it works for you!

stitchlibar commented 3 years ago

Fixed in the latest version.