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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Handling of // synopsys translate_off/on #170

Closed stitchlibar closed 3 years ago

stitchlibar commented 3 years ago

SV2V seems simply remove //synopsys translate_off/on micros and keep the code between. Is there an option to remove this portion of code after conversion?

zachjs commented 3 years ago

For the same reasons mentioned in https://github.com/verilator/verilator/issues/24, sv2v does not (and almost certainly will not) provide any special handling for such vendor-specific comments. I strongly encourage switching to ifdefs, which are principled and portable.

stitchlibar commented 3 years ago

Thanks. I will try ifdef