zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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2nd expression of procedural for-loop is not constant from Yosys #171

Closed stitchlibar closed 3 years ago

stitchlibar commented 3 years ago

Seems Yosys doesn't like the result of SV2V. It complains 2nd expression of procedural for-loop is not constant from Yosys

 for(int i=7;i>=sign;i--) begin
    somefun[i]  = 1'b0;
 end

Check the attached SysV line 18 for detail. test_copy.txt

stitchlibar commented 3 years ago

On correction. The complained non-constant is actually a constant when the parent is passing the argument. Please discard test_copy.txt and check test_copy2.txt test_copy2.txt

zachjs commented 3 years ago

This is a limitation of Yosys. You may be able to work around it by replacing

for(int i=7;i>=sign;i--) begin
    somefun[i] = 1'b0;
end

with

somefun[sign:7] = 1'b0;

The latest Yosys master has some improvements to the handling of constant function arguments, but they don't help in this particular case. Additionally, if you use the latest Yosys master, I believe you will run into the issue fixed by https://github.com/YosysHQ/yosys/pull/2716.

stitchlibar commented 3 years ago

Great suggest! Is it ok to be somefun[7:sign] = '0;

zachjs commented 3 years ago

Correction: You should probably use somefun[sign-:7] = '0; as the LRM does not permit non-constant expressions for non-indexed range bounds. You could also consider using localparams to define SIGN if the value is truly constant.

stitchlibar commented 3 years ago

It works.