search

zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
561 stars 55 forks source link

Error in two dimension array conversion #172

Closed stitchlibar closed 3 years ago

stitchlibar commented 3 years ago

SV2V leaves some two dimension arrays not converted. And it causes assignment error when a two-dimension array is assigned to one-dimension bus. // Only one two-d array is converted, and leave the other 4 untouched test_copy3.txt

   wire [8:0] isiga;
    wire [2:0] isigb [2:0];
    wire [2:0] isigc [2:0];
    wire [2:0] isigd [2:0];
    wire [2:0] isige [2:0];

    assign twod = (in0[0] ? isiga : (in0[1] ? isigb : (in1[0] ? isigc : (in1[1] ? isigd : isige))));
zachjs commented 3 years ago

Thanks for reporting this issue! It should be fixed as of 9acdb848c9027c2acd95289618669c6a352f3c29.

stitchlibar commented 3 years ago

Works great! Thanks!