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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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wire assignment is removed #175

Closed stitchlibar closed 3 years ago

stitchlibar commented 3 years ago

The following module is empty after conversion. SV2V ignores "wire estart = start&enable;". Changing to assign would work. test_wireonly.txt

module wiremod #(parameter abc = 1) (/AUTOARG/ // Outputs estart, // Inputs enable, start ); input enable, start; output estart; //assign works, wire doesn't //assign estart = start & enable; wire estart = start & enable; endmodule

zachjs commented 3 years ago

sv2v does not yet have good handling for port declarations split in this wag. It may take a few days before I have this properly supported.

stitchlibar commented 3 years ago

It is loosely written, if Design Compiler never spoiled the designers by throwing errors in the beginning. Thanks and take your time.

stitchlibar commented 3 years ago

Such statement can be always converted to one wire and one assign, right? wire estart = start & enable; ---> wire estart; assign estart = start & enable;

zachjs commented 3 years ago

Yes, those two formulations are equivalent.

zachjs commented 3 years ago

Sorry for the delay in getting this issue fixed! It should be fixed in 95c2bc996c2472a749fb23b2521b88ef6e041584. Please let me know if it works for you!

stitchlibar commented 3 years ago

Yes, it has been fixed. Great work!