zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Failure to parse deferred assertion with final #177

Closed saw235 closed 3 years ago

saw235 commented 3 years ago

The following passes

module xyz();
always_comb begin
        z1: assert final (x == y || z);
end
endmodule

but just this fails

module xyz();
        z1: assert final (x == y || z);
endmodule

Even though assertions item is part of the module common item, which covers deferred_immediate_assertion_item Reference : ieee 1800-2017 image image

zachjs commented 3 years ago

Thank you for your fix in #178!