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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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conversion error for case with empty default #183

Closed tinebp closed 3 years ago

tinebp commented 3 years ago

case X: value; Y: value; default: begin assert(false); end encase

Converts to:

case X: value; Y: value; default: encase

but should be:

case X: value; Y: value; default:; encase

zachjs commented 3 years ago

I believe this is the same issue and fix as in #184.

zachjs commented 3 years ago

Closing for the same reason as in #184: fixed and otherwise inactive.