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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Unable to convert an array of named constants in an enum #191

Closed kauser-rl closed 2 years ago

kauser-rl commented 2 years ago

Try to convert a legal SV typedef enum below. I'm using v0.0.9-0-gc822d2e.

package test1_pkg;
   typedef enum logic[8:0] {
     A[2]   = 9'h004,
     B[2]   = 9'h006,
     C[16]  = 9'h0a0,
     D      = 9'h123,
     E[4]   = 9'h124,
     UNUSED = 9'hF00
   } test_t;

endpackage // test1_pkg
zachjs commented 2 years ago

sv2v doesn't yet support this feature, but I can add it! I'll update here within a few days.

zachjs commented 2 years ago

I've pushed support for enumerated type ranges. Please give it a shot and let me know if it works for you!

Note that 9'hF00 in the above example is rejected by sv2v because the digits make up 12 bits, in excess of the explicitly given width of 9.

kauser-rl commented 2 years ago

I seem to have hit an error trying to build from the latest cloned version of the repo. Is it possible to generate a binary for Ubuntu 20.04?

zachjs commented 2 years ago

Please try running one of the uploaded artifacts on the latest workflow runs: https://github.com/zachjs/sv2v/actions. Those binaries are produced in the same manner as the official releases.

kauser-rl commented 2 years ago

Downloaded the Linux artifact and tested on my database. It seems to work as expected. Thanks.