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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Error in parsing System Verilog assertion #195

Closed mikhailmoiseev closed 2 years ago

mikhailmoiseev commented 2 years ago

sv2v reports: "Parse error: unexpected token '[' (Sym_brack_l)" for the following assertion:

sctAssertLine89 : assert property (
    @(posedge clk) |s |-> ##[1:5] |s_d );

Suppose it does not accept time interval in the assertion.

zachjs commented 2 years ago

I've added support for cycle delay ranges. Please let me know if it works for you!

mikhailmoiseev commented 2 years ago

It works well. Thank you.