interface instance syntax error

MoonbaseOtago commented 2 years ago

interface instances without connection lists fail with a syntax error - this is valid (for examples: https://www.chipverify.com/systemverilog/systemverilog-interface )

For example if I create:

interface fred;
    bit molly;
endinterface

module .....

       fred inst;
 ...
 endmodule

I get an error, if I instantiate "fred inst{}; I don't get the syntax error

zachjs commented 2 years ago

As far as I can tell, the connections on an instantiation are not optional. From the IEEE 1800-2017 grammar:

interface_instantiation ::=  interface_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance } ;
hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] )
name_of_instance ::= instance_identifier { unpacked_dimension }

I tried the following in all of the commercial tools available on edaplayground.com, and none of them allow it. A few produce an error that suggests parens could be missing.

interface intf;
endinterface

module mod(intf i);
endmodule

module top;
  intf i;
  mod m(i);
endmodule

sv2v produces an error like: Modport not in port list: intf i. Is this an interface missing a port list? Are there tools which allow this syntax?

zachjs commented 2 years ago

https://www.chipverify.com/systemverilog/systemverilog-interface

The relevant example I found there is also not accepted by any commercial tool as far as I can tell. There is also at least one other typo, so I'm not convinced that these examples should be taken as gospel.

zachjs commented 2 years ago

@MoonbaseOtago I'm still very interested to fix sv2v's behavior if there is an issue here. Am I missing something regarding the above examples?

zachjs / sv2v

interface instance syntax error #201