zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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arrays of instances not supported #202

Closed MoonbaseOtago closed 2 years ago

MoonbaseOtago commented 2 years ago

Arrays of interfaces are a thing, they're useful in generate for loops - and don't seem to be accepted

interface fred;
    bit molly;
endinterface

module .....

       fred inf[0:1];

       generate
                 for (i = 0; i < 2; i=i+1) begin
                       mod1  inst1(inf[I]); // hook up instances 
                       mod2  inst2(inf[I]);
                 end
       endgenerate
 ...
 endmodule
zachjs commented 2 years ago

It's not clear to me from the example whether fred inf[0:1]; is intended to be an interface port for the unnamed module (seems unlikely), or if it is supposed to be an instantiation of an array of fred (but the () are missing). Both of those features are supported, so I think I'm missing something here.

MoonbaseOtago commented 2 years ago

here's what's actually failing I have:

PMP #(.NUM_PMP(NUM_PMP), .NPHYS(NPHYS))pmp[0:1];

it doesn't like

PMP #(.NUM_PMP(NUM_PMP), .NPHYS(NPHYS))pmp()[0:1];

either PMP is defined:

interface PMP #(parameter NUM_PMP=16, NPHYS=56); bit [NUM_PMP-1:0]valid; // sadly arrays of buses aren't well supported bit [NUM_PMP-1:0]locked; // so we need to get verbose - unused wires will be optimised bit [NPHYS-1:2]start[0:NUM_PMP-1]; // out during synthesis bit [NPHYS-1:2]aend[0:NUM_PMP-1]; bit [2:0]prot[0:NUM_PMP-1]; endinterface

MoonbaseOtago commented 2 years ago

BTW this (and instantiations without port lists) work happily in verilator

MoonbaseOtago commented 2 years ago

Ah - I have the () in the wrong place

 PMP #(.NUM_PMP(NUM_PMP), .NPHYS(NPHYS))pm()[0:1];

fails

PMP #(.NUM_PMP(NUM_PMP), .NPHYS(NPHYS))pm[0:1]();

is OK not sure that's obvious :-) and neither way is obviously correct