signed to unsigned conversion in struct members causes trouble with >>>

[siquus]

Hi, thanks a lot for the tool! Here's the problem I experienced: System Verilog:

typedef struct packed {
        logic [10:0] Exp;
        logic signed [53:0] Mant;
    } normalSigned_t;

normalSigned_t double;
logic signed [54:0] shiftedLargerMant;

always_comb shiftedLargerMant = {double.Mant[53], double.Mant >>> Shift};

sv2v changes the assignment to always_comb shiftedLargerMant = {double[53], double[53-:54] >>> Shift}; That is the arithmetic shift will now interpret the left operand as unsigned and work the same as regular shift.

My quickfix for now is introduce an unnecessary $signed() to the original System Verilog always_comb shiftedLargerMant = {double.Mant[53], $signed(double.Mant) >>> Shift};

Thanks!

[zachjs]

This is a great catch. Thank you for filing this issue! I've just pushed a fix. Can you confirm it's working for you?

[siquus]

That fix looks familiar :-)

Works on my desk - kudos for your fast reaction time!