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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Parse error: missing expected `endfunction` #209

Closed hello-eternity closed 2 years ago

hello-eternity commented 2 years ago

hello ,my sv file have such part

function [ROB_PC_OFFSET_WIDTH-1:0] get_pc_offset;
        input [VADDR_WIDTH-1:0] pc_i;
        assign get_pc_offset = pc_i[1 +: ROB_PC_OFFSET_WIDTH];
    endfunction : get_pc_offset

and got an error at the third line. rvh_rcu_pkg.sv:63:9: Parse error: missing expectedendfunction` here is the file [rvh_rcu_pkg.sv.zip](https://github.com/zachjs/sv2v/files/9036632/rvh_rcu_pkg.sv.zip) command is sv2v rvh_rcu_pkg.sv -w rvh1.v`

zachjs commented 2 years ago

Although this feature is not in the latest release, the version on master supports procedural continuous assignments. Can you give that a try?

zachjs commented 2 years ago

Did upgrading fix this issue for you?

hello-eternity commented 2 years ago

Yes, the master version sovle this problem. Thank you very much.