Closed hello-eternity closed 2 years ago
This would require some form of logical equivalence checking or formal verification. Others have used commercial tools. You can see a (potentially outdated) example at https://github.com/lowRISC/ibex/blob/ea4e938/syn/lec_sv2v.sh.
Thank you.
Is there any way to judge whether the converted verilog file is equivalent to the previous system Verilog file?