zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Don't support sequence #214

Closed hello-eternity closed 1 year ago

hello-eternity commented 1 year ago

https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim/rtl/prim_alert_sender.sv sv2v this file and fail at 301 sequence

zachjs commented 1 year ago

I've made a branch seqprop which attempts to add support for sequence and property declarations. Can you let me know if that works for you?

hello-eternity commented 1 year ago

Not really, In fact it got an error at 302 line.(before is 301 line )

301.           sequence PingSigInt_S;
302.                    alert_rx_i.ping_p == alert_rx_i.ping_n [*2];
303.           endsequence

Error log, seems from other reason. ../prim_alert_sender.sv:302:46: Parse error: unexpected token '[*' (Sym_brack_l_aster)

zachjs commented 1 year ago

Can you help me understand your overall goal here? What downstream frontend are you targeting?

Although sv2v already supports some basic syntax for assertions, it removes them by default, though it can pass them through if requested (-E assert).

For those using sv2v as part of a synthesis flow, complex assertions unsupported or unneeded downstream are sometimes disabled entirely via a macro. In OpenTitan, assertions can be disabled by defining SYNTHESIS. Many tools, including sv2v, allow setting preprocessor macros on the command line via -D.

hello-eternity commented 1 year ago

ok, thank you very much for your answer, the problem about the sequence itself has indeed been solved, I'm sorry that I don't know much about this assert problem is removed by default, so I said this errors encountered, thank you very much for sv2v contribution