Array manipulation methods

[daglem]

It seems like the following is not implemented by any open source tool: IEEE Std 1800™-2017 7.12 Array manipulation methods.

I don't know whether it is even theoretically possible to generate Verilog code for this, however perhaps it can be taken as a challenge :-)

The syntax seems quite elegant, and could considerably improve code in some cases. Here is an example, where approximately 50 lines could have been reduced to 1, if I understand correctly:

https://github.com/daglem/reDIP-SID/blob/master/gateware/sid_dac.sv

[daglem]

Learning some more Verilog, I realized that e.g. array reduction can be done along the lines of the following:

item_t _sum[array.size];

for (genvar i = 0; i < array.size; i++) begin
    always_comb
        _sum[i] = (i == 0 ? 0 : _sum[i - 1]) + (with_expr ? _sum[i] : 0);
end

always_comb
    res = _sum[array.size - 1];

So, I guess it may be possible to implement most, if not all, of the array manipulation methods using plain Verilog. However since this feature is probably not used much, and workarounds like the above seem simple enough, perhaps it's not worth the trouble?