zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Unknown bindings port connections #222

Closed hello-eternity closed 1 year ago

hello-eternity commented 1 year ago

Sorry, I can't find the bug in detail, and here is my error log Do I need to change some syntax?

sv2v: unknown bindings "rt_cid_delta_seed_i", "rt_cid_base_seed_i" specified for port connections in instance "rubytest_top_u" of "rubytest_top"
CallStack (from HasCallStack):
  error, called at src/Convert/ResolveBindings.hs:111:9 in main:Convert.ResolveBindings

here is my code and the top is top.sv

code.zip

zachjs commented 1 year ago

sv2v preprocesses files in the order in which they are specified, in line with other tools I have encountered. In this case, the macro definitions in rubytest_define.sv need to be processed before any files which depend on them. Thus sv2v *.sv produces the error above, but sv2v rubytest_core.sv *.sv seems to work as expected. Please let me know if this works for you!

The portions of the relevant files are processed in the order below when using sv2v *.sv, leading to the unknown port connection which sv2v was complaining about.

rubytest_core.sv:

...
`ifdef RT_MODE_CLASSIC
,input logic [RT_CID_DELTA_NUM_W-1:0] rt_cid_delta_seed_i//2
,input logic [RT_CHECK_NUM_W-1:0] rt_cid_base_seed_i//5
`else
,input logic [RT_CHECK_GEN_ADDR_W-1:0] rt_info_addr_seed_i
,input logic [$bits(lsu_op_e)-1:0]     rt_info_opcode_seed_i
`endif
...

rubytest_define.sv:

...
`define RT_MODE_CLASSIC
...

top.sv:

...
  `ifdef RT_MODE_CLASSIC
    .rt_cid_delta_seed_i        (_rt_cid_delta_seed),
    .rt_cid_base_seed_i         (_rt_cid_base_seed),
  `else
    .rt_info_addr_seed_i        (_rt_info_addr_seed),
    .rt_info_opcode_seed_i      (_rt_info_opcode_seed),
  `endif
...
hello-eternity commented 1 year ago

That worked! Thank you for your patience