Can't resolve function name

flaviens commented 1 year ago

Hi!

I first posted the issue in Yosys and apparently it is an sv2v issue so I open it here.

Version

sv2v v0.0.10-1-gc00f508

On which OS did this happen?

Linux

Reproduction Steps

Requires Yosys and sv2v (tested with Yosys 0.22+29 (git sha1 12267a098, gcc 11.2.0 -fPIC -Os) and sv2v v0.0.10-1-gc00f508).

git clone https://github.com/bsg-external/HardFloat.git
cd HardFloat/source
sv2v -IRISCV mulAddRecFN.v -w sv2v_out.v
yosys -p 'read_verilog -defer -sv sv2v_out.v; hierarchy -top mulAddRecFNToRaw -check'

Expected Behavior

No error related to mulAddRecFNToRaw.clog2.

Actual Behavior

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.22+29 (git sha1 12267a098, gcc 11.2.0 -fPIC -Os)

-- Running command `read_verilog -defer -sv sv2v_out.v; hierarchy -top mulAddRecFNToRaw -check' --

1. Executing Verilog-2005 frontend: sv2v_out.v
Parsing SystemVerilog input from `sv2v_out.v' to AST representation.
Storing AST representation for module `$abstract\mulAddRecFNToRaw_preMul'.
Storing AST representation for module `$abstract\mulAddRecFNToRaw_postMul'.
Storing AST representation for module `$abstract\mulAddRecFNToRaw'.
Storing AST representation for module `$abstract\mulAddRecFN'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

3. Executing AST frontend in derive mode using pre-parsed AST for module `\mulAddRecFNToRaw'.
Generating RTLIL representation for module `\mulAddRecFNToRaw'.
sv2v_out.v:386: ERROR: Can't resolve function name `\mulAddRecFNToRaw.clog2'.

Thanks!

zachjs commented 1 year ago

Thanks for reporting this! I've pushed a fix to prevent this issue in such cases. Because it used a hierarchical identifier within a constant expression, sv2v's previous output was indeed illegal per the IEEE standards, though some tools do not impose this restriction. Please let me know if the fix works for you!

flaviens commented 1 year ago

Cool thanks! (haven't tested the patch thoroughly though).

Thank you very much for you help! Flavien

zachjs / sv2v