zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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data type `string` not removed from parameter #224

Closed patrickrst closed 1 year ago

patrickrst commented 1 year ago

Input:

module sample #(
    parameter string IMPL = "ram"
);
endmodule

Output:

module sample;
        parameter string IMPL = "ram";
endmodule

iverilog gives the error:

$ iverilog sample.v
sample.v:2: error: parameter declared outside parameter port list must have a default value.
sample.v:2: syntax error
sample.v:2: error: invalid module item.

I believe that string has to be removed for Verilog compatibility?

zachjs commented 1 year ago

Thank you for pointing out this issue! I agree the string data type should be removed in such cases. I've pushed a simple new conversion phase to do so. Please let me know if it works for you.

patrickrst commented 1 year ago

Works great, thank you for taking the time to fix this!