Why converted module's name has '~' character ?

zachjs / sv2v

SystemVerilog to Verilog conversion

BSD 3-Clause "New" or "Revised" License

540 stars 52 forks source link

Why converted module's name has '~' character ? #225

Closed forthyen closed 1 year ago

forthyen commented 1 year ago

module ~rr_arb_tree_369C9 ( clk_i, rst_ni, flush_i, rr_i, req_i, gnt_o, data_i, req_o, gnt_i, data_o, idx_o ); parameter type DataType_TagType_TagType_DataWidth_type;

forthyen commented 1 year ago

I clone latest source code and rebuild sv2v, then solve this problem!