Why "sv2v: src\Convert\TypeOf.hs:417:11-37: Non-exhaustive patterns in (tf, _ : rs)" ?

zachjs / sv2v

SystemVerilog to Verilog conversion

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Why "sv2v: src\Convert\TypeOf.hs:417:11-37: Non-exhaustive patterns in (tf, _ : rs)" ? #227

Closed forthyen closed 1 year ago

forthyen commented 1 year ago

sv2v -v cv32e40xx.sv

and then

sv2v: src\Convert\TypeOf.hs:417:11-37: Non-exhaustive patterns in (tf, _ : rs)

cv32e40xx.zip

forthyen commented 1 year ago

Sorry! I add -DMAIN_CORE_CV32E40X and modify source. Upload it again !

cv32e40xx.zip

zachjs commented 1 year ago

@forthyen Is there an issue you're still facing here? Even if a failure like this is caused by an error in the source (it might be not be!), I think sv2v should be able to do a better job communicating that issue to the user.

I can reproduce the failure locally. If you have a workaround, it would be great to know more, especially if others run into a similar issue.