problem with the transaltion of ibex

[ourspalois]

Hi, I am a intern in a lab in france a i am curently trying to run ibex on a terasic card. This means I have to use quartus and it's support of SystemVerilog is poor. So I am trying to translate the SystemVerilog of ibex to a verilog that quartus standart might understand. And in doing so the parser returns an error on "\" in `defines. as an "unexpected tokens

to be more precise here is an example : the sv code :

`define PRIM_FLOP_SPARSE_FSM(__name, __d, __q, __type, __resval = `PRIM_FLOP_RESVAL, __clk = `PRIM_FLOP_CLK, __rst_n = `PRIM_FLOP_RST, __alert_trigger_sva_en = 1)
  `ifdef SIMULATION                                   \
    prim_sparse_fsm_flop #(                           \
      .StateEnumT(__type),                            \
      .Width($bits(__type)),                          \
      .ResetValue($bits(__type)'(__resval)),          \
      .EnableAlertTriggerSVA(__alert_trigger_sva_en), \
      .CustomForceName(`PRIM_STRINGIFY(__q))          \
    ) __name (                                        \
      .clk_i   ( __clk   ),                           \
      .rst_ni  ( __rst_n ),                           \
      .state_i ( __d     ),                           \
      .state_o (         )                            \
    );                                                \
    `PRIM_FLOP_A(__d, __q, __resval, __clk, __rst_n)  \
    `ASSERT(``__name``_A, __q === ``__name``.state_o) \
  `else                                               \ ( <- THIS ONE)
    prim_sparse_fsm_flop #(                           \
      .StateEnumT(__type),                            \
      .Width($bits(__type)),                          \
      .ResetValue($bits(__type)'(__resval)),          \
      .EnableAlertTriggerSVA(__alert_trigger_sva_en)  \
    ) __name (                                        \
      .clk_i   ( __clk   ),                           \
      .rst_ni  ( __rst_n ),                           \
      .state_i ( __d     ),                           \
      .state_o ( __q     )                            \
    );                                                \
  `endif

the backslash not recognised is the one before the marker (<- THIS ONE)

i used the command : sv2v --write=/some/dir/test.v ibex_top.sv which seems correct to me. and got the error : ./prim_flop_macros.sv:60:55: Parse error: unexpected token '\' (Unknown)

seems to me this code is valid and is just to be treated as an include (I just started sv this monday so I am not quite sure) I checked the standart too and didn't see the problem.

If you want i can provide more examples of errors generated. (they are all pretty similar)

Please tell me if this is a bug or if I mis-used your tool.

Thanks,

[zachjs]

1. What exact version of sv2v are you using? Please check sv2v --version.
2. What is the exact command line you are using? For me, converting ibex_top.sv alone (correctly) fails because of the unresolved references to ibex_pkg.

[ourspalois]

my version is sv2v v0.0.10-13-geca8714

to get a file containing all of the rtl files I run a fusesoc command : fusesoc --cores-root . run --target=lint --setup --build-root ./build/ibex_out lowrisc:ibex:ibex_top

then extract all the rtl files in the build directory then i run sv2v on the ibex_top.sv and it finds the files but triggers on code that looks fine to me

I just tried to run the code under vivado as is and i get errors on the same points so I think this is an IBEX problem and sv2v is fine.

If you want you can close the topic and/or delete it. Thanks for your answer and sorry for the false alarm.

[ourspalois]

update : now works under vivado, the problem was due to a bad fusesoc target (change to synth)

Thanks ! and sorry for the issue ^^'''