zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Missing empty port connection in output file #234

Closed Risto97 closed 1 year ago

Risto97 commented 1 year ago

Hello, I am not sure if it's by design but I feel like it might be a bug.

module submod(
    input wire one,
    output wire two
);
endmodule

module test_top;
    wire one;

    submod submod(
        .one(one),
        .two()
    );
endmodule

Produces:

module submod (
        one,
        two
);
        input wire one;
        output wire two;
endmodule
module test_top;
        wire one;
        submod submod(.one(one));
endmodule

As you can see empty port connection .two() is missing from the instantiation submod.

zachjs commented 1 year ago

Thanks for reporting this! I've fixed it in 6c4ee8f4bc399262fe0ea2e0873538dcdae23aa7. Can you give it a try?

Risto97 commented 1 year ago

Yes, I can confirm its fixed. Thanks