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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Fixing a bug where always_* are not converted when attributed #238

Closed dwRchyngqxs closed 1 year ago

dwRchyngqxs commented 1 year ago

Everything is in the title. Example triggering the bug

module top();
  wire a;
  (* test *) always_comb a = 1;
endmodule

There is a test folder in which this test might be worth adding, which subdirectory should I add it in?

zachjs commented 1 year ago

Thank you for splitting this out!

Your test should go in test/core/always_attr.sv and there should be a corresponding .v reference Verilog that behaves equivalently. Other tests in that folder can provide examples of what's possible under the setup, stylistic conventions, etc. You can run a subset of a suite of tests with ./run.sh.

Could you also add the following to the changelog? Fixed an issue that left `always_comb`, `always_latch`, and `always_ff` unconverted when tagged with an attribute.

dwRchyngqxs commented 1 year ago

I ran make coverage to make sure the code I added is covered by the test I added (I had to compile iverilog from the commit indicated by the CI). This PR should be ready to be merged.

zachjs commented 1 year ago

Thank you again for this contribution! I greatly appreciate the effort.

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