zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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`parameter type`s for `interface`s not working with types that have been defined using `typedef` #248

Closed fl4shk closed 1 year ago

fl4shk commented 1 year ago

I get this error:

sv2v: interface param DataT expected type, found expr: alu_pkg_Vec2T CallStack (from HasCallStack): error, called at src/Convert/Interface.hs:504:36 in main:Convert.Interface

`timescale 1ns/1ps
`default_nettype none

package alu_pkg;
    //--------
    localparam int unsigned VEC2_ELEM_WIDTH = 8;
    typedef struct packed {
        logic [VEC2_ELEM_WIDTH - 1:0] x, y;
    } Vec2T;

    localparam int unsigned OP_WIDTH = 2;
    typedef enum logic [OP_WIDTH - 1:0] {
        OP_ADD,
        OP_ADC,
        OP_SUB,
        OP_SBC
    } OpT;
    //--------
endpackage

interface AluIntf
#(
    parameter type DataT
);
    //--------
    DataT inp_a, inp_b;
    logic inp_carry;
    alu_pkg::OpT inp_op;
    //--------
    DataT outp_data;
    logic outp_carry;
    //--------
endinterface

module Alu
//#(
//  parameter type DataT
//)
(
    //AluIntf #(.DataT(DataT)) intf
    AluIntf intf
);
    always_comb begin
        case (intf.inp_op)
        //--------
        alu_pkg::OP_ADD: begin
            {intf.outp_carry, intf.outp_data}
                = {1'b0, intf.inp_a} + {1'b0, intf.inp_b};
        end
        alu_pkg::OP_ADC: begin
            {intf.outp_carry, intf.outp_data}
                = {1'b0, intf.inp_a} + {1'b0, intf.inp_b}
                    + {{$size(intf.inp_a){1'b0}}, intf.inp_carry};
        end
        alu_pkg::OP_SUB: begin
            {intf.outp_carry, intf.outp_data}
                = {1'b0, intf.inp_a} + {1'b0, ~intf.inp_b}
                    + {{$size(intf.inp_a){1'b0}}, 1'b1};
        end
        alu_pkg::OP_SBC: begin
            {intf.outp_carry, intf.outp_data}
                = {1'b0, intf.inp_a} + {1'b0, ~intf.inp_b}
                    + {{$size(intf.inp_a){1'b0}}, intf.inp_carry};
        end
        //--------
        endcase
    end
endmodule

module Top
(
    input logic [(alu_pkg::VEC2_ELEM_WIDTH * 2) - 1:0] inp_a, inp_b,
    input logic inp_carry,
    input alu_pkg::OpT inp_op,
    output [(alu_pkg::VEC2_ELEM_WIDTH * 2) - 1:0] outp_data,
    output logic outp_carry
);
    AluIntf #(.DataT(alu_pkg::Vec2T)) alu_intf();

    assign {
        alu_intf.inp_a, alu_intf.inp_b, alu_intf.inp_carry, alu_intf.inp_op
    } = {
        inp_a, inp_b, inp_carry, inp_op
    };
    assign {outp_data, outp_carry} = {
        alu_intf.outp_data, alu_intf.outp_carry
    };

    Alu alu(.intf(alu_intf));
endmodule
fl4shk commented 1 year ago

a potential workaround may be to just put the type definition in a `define

fl4shk commented 1 year ago

Wait a minute, I just realized my installation of sv2v was out of date! I'll update it.

fl4shk commented 1 year ago

good news, updating my sv2v installation fixes this issue!

fl4shk commented 1 year ago

Closing issue