Array literals flow into Verilog unchanged

[YikeZhou]

Edit: Could it be because the feature is not synthesizable (all the time)? Apologize if this is a "won't fix".

Input:

module top(output logic[7:0] o);
   assign o = '{0:1, 3:1, 7:1, default:0};
endmodule

Output:

module top (o);
        output wire [7:0] o;
        assign o = '{
                0: 1,
                3: 1,
                7: 1,
                default: 0
        };
endmodule