`input reg` is not allowed in Verilog

[YikeZhou]

It appears that sv2v cannot handle the input reg in SystemVerilog, which results in invalid Verilog code.

Example input:

module top(
    input reg [15:0]x,
    input reg [15:0]y,
    output reg [15:0]r
);

endmodule

Output:

module top (
    x,
    y,
    r
);
    input reg [15:0] x;
    input reg [15:0] y;
    output reg [15:0] r;
endmodule

[zachjs]

Thanks for pointing this out! I believe your interpretation of the spec is correct. This is addressed in 2579bc8302522bd058765d4e08d45fc4f959b65b. Please let me know if it works for you!

[zachjs]

I believe this issue is resolved. Please feel free to reopen it if you're still running into problems.