Hello. Thanks for all the work done for this tool!
I am trying to create cleaner netlist views for my SystemVerilog code. One way I'm imagining this is through some functionality that converts procedural blocks to modules. This way, a graph viewer can hide a complex always_comb block behind a module black box. A user could provide a list of begin...end block names they want converted.
My current flow is SystemVerilog->sv2v->yosys->netlistsvg.
I'm wondering if it could make sense for sv2v to implement this feature. (Maybe instead it should be a Yosys plugin). I am interested to hear if you think this would be a valuable addition to sv2v.
Hello. Thanks for all the work done for this tool!
I am trying to create cleaner netlist views for my SystemVerilog code. One way I'm imagining this is through some functionality that converts procedural blocks to modules. This way, a graph viewer can hide a complex
always_combblock behind a module black box. A user could provide a list ofbegin...endblock names they want converted.My current flow is SystemVerilog->sv2v->yosys->netlistsvg.
I'm wondering if it could make sense for sv2v to implement this feature. (Maybe instead it should be a Yosys plugin). I am interested to hear if you think this would be a valuable addition to sv2v.