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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Support for `unique` and `priority` #270

Closed sifferman closed 6 months ago

sifferman commented 8 months ago

Hello!

In my opinion, if unique or priority statements are used on case statements, sv2v should add the attributes parallel_case and full_case, respectively.

This is consistent with Vivado: https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Case-Statement

From the IEEE 1364.1-2002 spec:

  • 6.1.1.1: (* synthesis, full_case *) shall inform the synthesis tool that for all unspecified case choices, the outputs assigned within the case statement may be treated as synthesis don’t-care assignments.
  • 6.1.1.2: (* synthesis, parallel_case *) is commonly used to remove priority encoders from the gate-level implementation of an RTL case statement.

I would be happy to work on a PR if you feel this would be a valuable addition to sv2v.