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zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Token '#' issue in wire definition and assignment #272

Closed stitchlibar closed 5 months ago

stitchlibar commented 5 months ago

Is such syntax legal? wire #1 mywire = anothewire;

Seems sv2v doesn't like the syntax, it has to be wire mywire; assign #1 mywire = anotherwire.

stitchlibar commented 5 months ago

It's not a valid syntax for synthesis. Some other synthesis tool seems not complaining. I guess we can use hack to remove it before processing. Close the issue.