Open sundeep2249 opened 2 months ago
What have you tried to this point? sv2v's README includes basic usage instructions. The output is intended to be Yosys-compatible.
Hi, Does these verilog files works on Intel quartus? I'm getting some errors after I install the stack and then using the make command
sundeepreddypambala@Sundeeps-MacBook-Air my-project % stack build sundeepreddypambala@Sundeeps-MacBook-Air my-project % cd sv2v sundeepreddypambala@Sundeeps-MacBook-Air sv2v % make mkdir -p bin stack install --install-ghc --local-bin-path bin
Does these verilog files works on Intel quartus?
I don't have access to Quartus, so I can't say for sure. However, I would be interested in fixing issues that affect the portability of sv2v's output. I do know there are other users who use sv2v's output as the input to commercial tools.
I'm getting some errors after I install the stack and then using the make command
Based on https://discourse.haskell.org/t/cabal-and-llvm-issue/3672/13, the version of the compiler sv2v was using (GHC 8.10.7) doesn't support compiling for Apple Silicon (aarch64-osx
) without using LLVM, which doesn't come preinstalled on macOS. However, never versions should have native support. I just pushed a changed to upgrade sv2v to a newer (though not the newest) version of the compiler (GHC 9.6.4). Please try running git pull
and then make
again.
The dependency on llvm seems to have gone away. There are some failures in the test suite, I don't know if expected or not.
With this latest version, sv2v compiles cva6(Ariane RISCV processor) correctly with one change:
diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 8b5998ae..6f9c8fc2 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -67,8 +67,8 @@ module acc_dispatcher output logic inval_valid_o, output logic [63:0] inval_addr_o, // Accelerator interface
input acc_pkg::accelerator_resp_t acc_resp_i );
`include "common_cells/registers.svh"
the significance of this is that acc_req_t and acc_resp_t are type parameters and as such get assigned at elaboration time, perhaps sv2v is trying to find the fields before elaboration (just speculation)
(when I say correctly I mean no error is produced before the output is generated, not that the output has been validated by me)
Hello,
Does sv2v tool converts system verilog files which includes another system verilog file?
@jrrk2:
.github/workflows/main.yaml
. I have just upgraded the iverilog version used in CI to their latest commit, fixing some compatibility issues over the past few days. Please pull and see if the tests pass with the new version.@sundeep2249 sv2v does support `include
. sv2v has pretty good support for most synthesizable and commonly-used language features. I encourage you to try it out and see if it works for you!
I pushed a pull request that demonstrates the problem with type parameters:
Can you let me know on how to convert system verilog to verilog for yosys