zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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add enum attributes to enum values #292

Open rroohhh opened 1 month ago

rroohhh commented 1 month ago

yosys and for example amaranth add enum_base_type and enum_value_{value} to variables that used to be enums a la

(* enum_base_type = "Port" *)
(* enum_value_000 = "Local" *)
(* enum_value_001 = "North" *)
(* enum_value_010 = "South" *)
(* enum_value_011 = "East" *)
(* enum_value_100 = "West" *)
(* src = "/data/projects/amaranth/amaranth/lib/stream.py:48" *)
wire [2:0] result__payload;
zachjs commented 1 month ago

Thanks for filing this issue! Are you looking to have these enum attributes for debugging, or do they result in some behavioral difference downstream?

rroohhh commented 1 month ago

Only for debugging, mainly to get the names in the waveform viewer.