Generate _sv2v_0 problem

[BoChen-Ye]

This is very good progrom！

However, it will generate some code that I don't need in FSM file. For example,

reg _sv2v_0;        
if (_sv2v_0)
;
initial _sv2v_0 = 0;

I don't know why.

[zachjs]

The SystemVerilog specification requires that always_comb blocks execute at time zero. sv2v uses _sv2v_0 to trigger the resulting always blocks at time zero. A couple ideas:

1. If your downstream flow supports SystemVerilog constructs like always_comb (Yosys does), then you can exclude the conversion of always_* by passing --exclude always to sv2v.
2. Depending on the other constructs in your design, you might be able to grep -v _sv2v_0 the output of sv2v to filter out these statements.