zachjs / sv2v

SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Conversion of '0 and '1 #93

Closed NilsGraf closed 4 years ago

NilsGraf commented 4 years ago

'0 and '1 are currently converted to 1'sb0 and 1'sb1, resp. The latter is not accurate for multi-bit assignments (because '1 actually means that all bits are set to 1, not just the LSB). And the former causes LEC issues when 1'sb0 drives a multi-bit input of a module (resulting in the upper input-bits being undriven).

Would it make sense to use the following translations instead?

See also this workaround. Thanks!

zachjs commented 4 years ago

Handling these "unbased unsized" literals has proven deceptively complex. In self-determined contexts (i.e., {'1, 'x}), they should behave as though they are a single bit. Otherwise, they fill the context-supplied size.

As far as I can tell 'd0 is exactly the same as 0, and -'sd1 is exactly equivalent to -1 (but not -'sb1). I recently added a hack to deal with the sizing associated with ternary expressions. Your suggestion of -'sd1 thankfully eliminates the need for that hack. However, I think to make this conversion work properly, it must be context aware, selecting either the sized or unsized replacement depending on where it is used..

NilsGraf commented 4 years ago

Awesome. I think mapping '0 and '1 onto 0 and -1 should also work fine.

zachjs commented 4 years ago

I think 8cfd05de1a821cc91986643b48249e637882b81f should be closer to what you're looking for. Please let me know if you find any issues.

zachjs commented 4 years ago

Has this issue been resolved?

NilsGraf commented 4 years ago

Yes, thanks!