SOLVED: Adder example hangs linux

[mikemccauley]

Hi. First, compliments on such a well structured and documented tutorial. I have followed it exactly as given, built linux, SD card and the FPGA examples, and the blink example works fine. But when I go on to the adder example, everything builds exactly as documented EXCEPT that when I finally run the adder program on the DE-10, linux hangs hard, and needs to be powered off and restarted.

Experiments in DBG show that the hang occurs when the adder C program attempts to access the HPS-to-FPGA (heavyweight) bus at this line: ((uint64_t )a_map) = a; Same hang if it tries to read from the sum (having previously removed the write to a and b).

Other experiments show that if the lightweight HPS-to-FPGA buses are not enabled in the device tree, the adder program gets a bus error instead of a hard hang.

Yes, I have followed your guidelines on what to do if your system hangs, and I have rebuilt everything many times, and double checked it until Im crosseyed :-)

I have also tried your further modified custom dts per https://github.com/zangman/de10-nano/issues/4

I know you wont be able to tell me from this what the problem is but my questions are:

1. I have read elsewhere that if the Platform Design is changed, it is necessary to regenerate the preloader. Is that correct? If so how should it be done for your example u-boot?
2. I read here https://digibird1.wordpress.com/playing-with-the-cyclone-v-soc-system-de0-nano-soc-kitatlas-soc/ that it is necessary (maybe?) to save some of the DDR RAM for the FPGA. Is that correct?
3. Is there some other step that I need to follow to enable access to the 'heavyweight' HPS-to-FPGA bus from linux?

[mikemccauley]

So after a 2 days of debugging I have the simple 64 bit adder example working. The problem with the example as given is that the example DE10_NANO_SoC_GHRD.v as given on https://github.com/zangman/de10-nano/wiki/Simple-Hardware-Adder:-Setting-up-the-Adder is missing one crucial line at the end of the soc_system u0(); clause. The missing line is for the hps_fpga_reset_n:

.hps_0_h2f_reset_reset_n(hps_fpga_reset_n),

without that line, linux hangs hard when the adder.c program first tries to access the heavyweight HPS_to_FPGA bus Interestingly, that line IS in the example DE10_NANO_SoC_GHRD.v at an earlier stage of the tutorial, per https://github.com/zangman/de10-nano/wiki/Simple-Hardware-Adder:-Initial-Project-Setup

I have attached the text of my corrected, working DE10_NANO_SoC_GHRD.v DE10_NANO_SoC_GHRD.txt

Im loading the .rbf file from linux at boot time if that is relevant. So it seems its not necessary to regenerate the preloader for the example adder to work, and I dont think the custom dts per #4 is necessary.

Thanks zangman for the example and tutorial.

[zangman]

Hey - so sorry for missing this. For some reason I'm not getting any notifications for issues raised here. I need to figure out what's wrong.

Thanks for finding this and fixing it. I may have missed this by accident. It definitely seems important, must have been carelessness on my part.

So it seems its not necessary to regenerate the preloader for the example adder to work, and I dont think the custom dts per #4 is necessary.

It will work without the dts. But I believe it's better to reserve some RAM and let Linux know that the memory is reserved for the FPGA. Otherwise there might be some other program using the same memory location (or the kernel itself) and there might be other nefarious bugs that arise.

[zangman]

Fixed it on the page that's missing it. Thanks for flagging it and sorry for the trouble you had to go through.

https://github.com/zangman/de10-nano/wiki/Simple-Hardware-Adder:-Setting-up-the-Adder

[lsyxiaopang]

I've encountered the same problem, and I found adding one line to the code may not fix the issue as we've deleted it in initial setup

However, when I skipped the initial setup it would work well