Closed wespiard closed 4 months ago
SystemVerilog
https://github.com/tree-sitter/tree-sitter-verilog
https://github.com/chipsalliance/verible/tree/master/verilog/tools/ls
SystemVerilog (newer version of Verilog) is a Hardware Description Language (HDL) used for digital design and verification.
Some common filetypes are .sv, .v, and .svh.
.sv
.v
.svh
UVM can support？
sqlmap3
commented
8 months ago sqlmap3
commented
8 months ago
Check for existing issues
Language
SystemVerilog
Tree Sitter parser link
https://github.com/tree-sitter/tree-sitter-verilog
Language server link
https://github.com/chipsalliance/verible/tree/master/verilog/tools/ls
Misc notes
SystemVerilog (newer version of Verilog) is a Hardware Description Language (HDL) used for digital design and verification.
Some common filetypes are
.sv,.v, and.svh.