zekeriyasari
commented
3 years ago Hi @YayeIrene
Since you did not provide me with your code, I could not understand the details of the system you are trying to simulate.
using take!(writer) the simulation get stuck at the run stage!
You may rarely use take!(writer) for your simulations! take! function is one of the core internal functions to make the data flow through the connections of the model. I am sure there must be something else to solve the problem, but I need to see your use case to elaborate!
Hoping that it helps, here is a minimum working example that simulates an RLC circuit driven by step source.
The block diagram model of a series RLC circuit is as below.
Here ds_rl is a dynamical system consisting of the series combination of the components resistor R and inductor L. ds_c is the dynamical system corresponding to capacitor C. The equations modeling the ds_rl` are
\dot{x}(t) = -R / L * x(t) + 1 / L * u(t)
y(t) = x(t)where x(t), u(t), y(t) are the state, input and output, respectively. The equations modelling ds_c are
\dot{x}(t) = 1 / C * u(t)
y(t) = x(t) So, here is the example code for the simulation of an RLC circuit (with component values R=1 Ohm, L=1 Henry, C=1 Farads).
using Causal
using Plots
@defmodel model begin
@nodes begin
gen = StepGenerator()
ds_rl = ODESystem(
righthandside = (dx, x, u, t) -> (dx[1] = -x[1] + u[1](t)),
readout = (x, u, t) -> x,
state = rand(1),
input = Inport(1),
output = Outport(1)
)
ds_c = ODESystem(
righthandside = (dx, x, u, t) -> (dx[1] = u[1](t)),
readout = (x, u, t) -> x,
state = rand(1),
input = Inport(1),
output = Outport(1)
)
adder = Adder(
signs = (+, -),
input = Inport(2),
output = Outport(1)
)
writer = Writer(
input = Inport(4)
)
end
@branches begin
gen[1] => adder[1]
adder[1] => ds_rl[1]
ds_rl[1] => ds_c[1]
ds_c[1] => adder[2]
gen[1] => writer[1]
ds_rl[1] => writer[2]
ds_c[1] => writer[3]
adder[1] => writer[4]
end
end
simulate!(model, 0., 0.01, 50.)
t, x = read(getnode(model, :writer).component)
plt = plot(layout=(2,2))
plot!(t, x[:, 1], label="u(t)", subplot=1, ylims=(0, 1.5))
plot!(t, x[:, 2], label="i(t)", subplot=2)
plot!(t, x[:, 3], label="v0(t)", subplot=3)
plot!(t, x[:, 4], label="vi(t) - v0(t)", subplot=4)Here are the simulation results.
YayeIrene
Hello, I am trying to simulate a power source which consists in a series capacitors banks which are discharged successively. Each capacitor bank is an RLC circuit with a switch. When the tension on the switch reaches 0 the capacitor is taken out of the circuit. My idea is to simulate with causal.jl. I have built the RLC circuit as an ode_system using @def_ode_system. This seems to work. (My next step will be to try to build it component by component!) I then created a model which has an RLC circuit node and other nodes necessary to compute the tension. I created also a callback, the condition is that the tension is zero. The tension is an output of an Adder component. I am having trouble accessing this value during simulation. using take!(writer) the simulation get stuck at the run stage! Is there a way to read the output of the Adder during simulation to be used by a callback condition function?
Thank you! Irene