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zephray / VerilogBoy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?
https://hackaday.io/project/57660-verilogboy
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PPU takes 176 clocks minimum to render a line rather than 172 on a real gameboy #2

Closed zephray closed 6 years ago

zephray commented 6 years ago

Not sure. Need further investigation. Leave it as is for now.

zephray commented 6 years ago

The reason for this is that the fetch unit takes 6 clocks to fetch 8 pixels while the pixel fifo takes 8 clocks to output 8 pixels, so 2 wait states are needed by the fetch unit. However in current implementation, this 2 wait states would be inserted no matter if the fifo is empty or not. Also there is also 2 additional wait states before entering the H-blank.